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| glossary:glossary_i [2022/01/26 10:40] – [Include Guard] WortingUK | glossary:glossary_i [2023/07/25 15:55] (current) – [ISR] add ISTR entry JohnFletcher |
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| Description used by UK track manufacturer, PECO, to denote turnouts manufactured with an insulated crossing (frog). This avoids the need for polarity switching for the crossing at the expense of poorer current collection for locomotives. | Description used by UK track manufacturer, PECO, to denote turnouts manufactured with an insulated common crossing, AKA frog. This avoids the need for polarity switching for the crossing at the expense of poorer current collection for locomotives. AKA dead frog. |
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| =====ISR===== | =====ISR===== |
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| An Interrupt Service Routine is a firmware/software program subroutine (sub-program) triggered by a microprocessor hardware pin. When triggered, the processor will temporarily execute a subroutine then return to the previous program execution. An ISR can be used to make the processor immediately take care of a time critical operation. While there are many uses for an ISR, some common uses would be for receiving serial bits from a serial data interface or sensing an external clock signal to trigger the sending of video signals at a precise time. In some cases there are more than one interrupt trigger pin or indication. Because of this there may be priority settings. A High priority interrupt cannot itself be interrupted whereas a Low priority interrupt can be interrupted by a High level one. This helps keep multiple ISRs from interfering with each other. | An Interrupt Service Routine is a firmware/software program subroutine (sub-program) triggered by a microprocessor hardware pin. When triggered, the processor will temporarily execute a subroutine then return to the previous program execution. An ISR can be used to make the processor immediately take care of a time critical operation. While there are many uses for an ISR, some common uses would be for receiving serial bits from a serial data interface or sensing an external clock signal to trigger the sending of video signals at a precise time. In some cases there are more than one interrupt trigger pin or indication. Because of this there may be priority settings. A High priority interrupt cannot itself be interrupted whereas a Low priority interrupt can be interrupted by a High level one. This helps keep multiple ISRs from interfering with each other. |
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| | =====ISTR===== |
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| | I seem to recall.... |
